Resistive random access memory (RRAM) is a type of nonvolatile memory. Generally, RRAM memory cells each include a resistive dielectric material layer sandwiched between two conductive electrodes. The dielectric material is normally insulating. However, by applying the proper voltage across the dielectric layer, a conduction path (typically referred to as a filament) can be formed through the dielectric material layer. Once the filament is formed, it can be “reset” (i.e., broken or ruptured, resulting in a high resistance state across the RRAM cell) and set (i.e., re-formed, resulting in a lower resistance state across the RRAM cell), by applying the appropriate voltages across the dielectric layer. The low and high resistance states can be utilized to indicate a digital signal of “1” or “0” depending upon the resistance state, and thereby provide a reprogrammable non-volatile memory cell that can store a bit of information.
FIG. 1 shows a conventional configuration of an RRAM memory cell 1. Memory cell 1 includes a resistive dielectric material layer 2 sandwiched between two conductive material layers that form top and bottom electrodes 3 and 4, respectively.
FIGS. 2A-2D show the switching mechanism of the dielectric material layer 2. Specifically, FIG. 2A shows the resistive dielectric material layer 2 in its initial state after fabrication, where the layer 2 exhibits a relatively high resistance. FIG. 2B shows the formation of a conductive filament 7 through the layer 2 by applying the appropriate voltage across the layer 2. The filament 7 is a conductive path through the layer 2, such that the layer exhibits a relatively low resistance across it (because of the relatively high conductivity of the filament 7). FIG. 2C shows the formation of a rupture 8 in filament 7 caused by the application of a “reset” voltage across the layer 2. The area of the rupture 8 has a relatively high resistance, so that layer 2 exhibits a relatively high resistance across it. FIG. 2D shows the restoration of the filament 7 in the area of the rupture 8 caused by the application of a “set” voltage across layer 2. The restored filament 7 means the layer 2 exhibits a relatively low resistance across it. The relatively low resistance of layer 2 in the “formation” or “set” states of FIGS. 2B and 2D respectively can represent a digital signal state (e.g. a “1”), and the relatively high resistance of layer 2 in the “reset” state of FIG. 2C can represent a different digital signal state (e.g. a “0”). The RRAM cell 1 can repeatedly be “reset” and “set,” so it forms an ideal reprogrammable nonvolatile memory cell.
One of the drawbacks of this type of RRAM memory cell is that the voltage and current needed to form the filament are relatively high (and could be significantly higher than the voltages needed to set and reset the memory cell).
To solve this issue, Applicants previously filed U.S. patent application Ser. No. 14/582,089, published as United States Patent Application Publication 2016/0181517, which is incorporated herein by reference. That application presented an improved RRAM memory cell that requires a lower voltage and current for forming the cell's filament. Specifically, that application disclosed a geometrically enhanced RRAM cell with electrodes and resistive dielectric layer configured in a manner that reduces the voltage necessary for forming the cell's conductive filament. Applicant had discovered that by providing a sharp corner in the resistive dielectric layer at a point between the two electrodes significantly reduces the voltage and current necessary to effectively form the filament. This design will be described below with reference to FIGS. 3-6.
FIG. 3 illustrates the general structure of RRAM memory cell 10, which includes a resistive dielectric layer 12 having elongated first and second portions 12a and 12b respectively that meet at a right angle. Specifically, first portion 12a is elongated and extends horizontally, and second portion 12b is elongated and extends vertically, such that the two portions 12a and 12b meet at a sharp corner 12c (i.e. resistive dielectric layer 12 has an “L” shape). The first electrode 14 is disposed above horizontal layer portion 12a and to the left of vertical layer portion 12b. The second electrode 16 is disposed below horizontal layer portion 12a and to the right of vertical layer portion 12b. Therefore, each of the first and second layer portions 12a and 12b are disposed between and in electrical contact with the electrodes 14 and 16. Electrodes 14 and 16 can be formed of appropriately conductive material such as W, Al, Cu, Ti, Pt, TaN, TiN, etc., and resistive dielectric layer 12 is made of a transition metal oxide, such as HfOx, TaOx, TiOx, WOx, VOx, CuOx, or multiple layers of such materials, etc.). Alternatively, resistive dielectric layer 12 can be a composite of discrete sub-layers with one or more sub-layers of transition metal oxides (e.g. layer 12 could be multiple layers: an Hf layer disposed between a TaOx layer and an HfOx layer). It has been discovered that filament formation through layer 12 at the sharp corner 12c can occur at lower voltages than if the dielectric layer 12 were planar due to the enhanced electric field at the sharp corner 12c. 
FIGS. 4A-4C show the steps in forming the inventive RRAM memory cell 10 and related circuitry. The process begins by forming a select transistor on a substrate 18. The transistor includes source/drain regions 20/22 formed in the substrate 18 and a gate 24 disposed over and insulated from the channel region there between. On the drain 22 is formed conductive blocks 26 and 28, and conductive plug 30, as illustrated in FIG. 4A.
A layer of conductive material 32 is formed over plug 30 (e.g. using photolithography techniques well known in the art). A block of conductive material 34 is then formed over just a portion of the layer of conductive material 32. The corner where layer 32 and block 34 meet can be sharpened by plasma treatment. Then, transition metal oxide layer 36 is deposited on layer 32 and on the vertical portion of block 34. This is followed by a conductive material deposition and CMP etch back to form a block of conductive material 38 on layer 36. The resulting structure is shown in FIG. 4B.
A conductive plug 40 is formed on conductive block 38. A conductive line (e.g. bit line) 42 is formed over and connected to plug 40. The resulting structure is shown in FIG. 4C. Layer 32 and block 34 form the lower electrode 16, layer 36 forms the resistive dielectric layer 12, and block 38 forms the upper electrode 14, of RRAM cell 10. FIG. 4C further contains a schematic representation for an RRAM memory cell, where the RRAM cell corresponds to RRAM cell 10 with its select transistor, and where BL is electrode 42, WL is electrode 24, and SL is electrode 20.
FIGS. 5A-5C show the steps in forming an alternate embodiment of the inventive RRAM memory cell 10 and related circuitry. The process begins by forming the select transistor on a substrate 18 as described above (source/drain regions 20/22 formed in the substrate 18, and gate 24 disposed over and insulated from the channel region there between). On the drain 22 is formed a conductive block 44, as illustrated in FIG. 5A.
A layer of conductive material 46 is formed over block 44. A transition metal oxide layer 48 is deposited on block 46, along one of the vertical side surfaces of block 46, and away from block 46. This is followed by forming a layer of conductive material 50 by deposition and CMP etch back. The resulting structure is shown in FIG. 5B. Hence, there exists a sharp tip corner 46a of material 46 that is pointing to another sharp tip corner intersection of layers 48/50. This enhances the localized field at top corner 46a which reduces the necessary forming voltage.
A conductive plug 52 is formed on conductive layer 50. A conductive line (e.g. bit line) 54 is formed over and connected to plug 52. The resulting structure is shown in FIG. 5C. Layer 46 forms the lower electrode 16, layer 48 forms the resistive dielectric layer 12, and layer 50 forms the upper electrode 14, of RRAM cell 10.
As a non-limiting example, RRAM cell 10 in its original state is shown in FIG. 6A. Electrodes 14 and 16 are formed of CU and resistive dielectric layer 12 is formed of HfOx. In order to form a conductive filament 56 through the sharp corner 12c as shown in FIG. 6B, a voltage difference of about 3-6V is applied across electrodes 14 and 16. In order to reset the RRAM cell 10 by forming a rupture 58 in filament 56 as shown in FIG. 6C, a voltage difference of about 1-4 V is applied across electrodes 14 and 16. In order to set the RRAM cell 10 by removing rupture 58 in filament 56 as shown in FIG. 6D, a voltage difference of about 1-4 V is applied across electrodes 16 and 14 (i.e. reverse polarity relative to forming and reset voltages).
Although RRAM cell technology is known in the prior art, what is needed are improved array architectures and layouts. What is further needed are improved circuits for performing read and write operations with respect to RRAM cells such as RRAM memory cell 1 and 10.